Design and Analysis of Quasi-Y Source High Gain DC/DC Resonant Converter for Renewable Energy Applications

Sugali Harinaik^* and Shelas Sathyan

National Institute of Technology Tiruchirappalli, Tamil Nadu, India
E-mail: Harinaik223@gmail.com; shelassathyan@yahoo.co.in
*Corresponding Author

Received 25 January 2022; Accepted 02 May 2022; Publication 03 January 2023

Abstract

This paper proposes a magnetically coupled partial resonant isolated quasi-Y source DC/DC converter. Here, to achieve soft switching, there is no additional auxiliary circuits or magnetic components are used. By making use of transformer’s parasitic elements like winding capacitance (C${\mathrm{p}}_{}$) and leakage inductance (L${\mathrm{k1}}_{}$), zero current switching (ZCS) is obtained at the turn-off instant of all MOSFETs. Hence, the converter can operate at a higher frequency, so that compact size and good efficiency are feasible. This converter inherits all the conventional impedance source converter features, and a higher gain is obtained by using three winding coupled inductor and isolation transformer with small shoot-through duty (d${\mathrm{ST}}_{}$). Hence, the continuous input current (CIC) and galvanic isolation feature of this converter is most suitable for renewable energy applications. Also, the output voltage is regulated by changing the switching frequency. Finally, a 300 W prototype is designed and tested in the laboratory. The simulation, experimental results with mathematical and design analysis are provided.

Keywords: Renewable energy resources, impedance source converters, high voltage gain, DC/DC converters, zero current switching (ZCS).

1 Introduction

Nowadays, demand for renewable energy resources is growing more popular due to extensive utilization of fossil fuels such as coal, gas, and oil. Hence, which leads to major environmental pollution, greenhouse gas emissions, and it has a significant global impact. However, there is a considerable mismatch between the availability of fossil fuels and energy demand. So to meet the energy demand and ecological concerns, renewable energy resources are best alternatives. These sources are mainly wind, Biomass, fuel cells, photovoltaic (PV) systems, etc. [1, 2]. Among these, Solar PV and Wind are good candidates because their universal availability, emission-free, and fuel cell are also most significant due to higher conversion efficiency. The output voltage of the aforementioned renewable energy resources is low, so to interface with DC grids, high step-up DC/DC converters are required [3]. High voltage gain can be achieved by using the traditional DC/DC boost converter. However, the converter needs to operate at higher duty (close to unity). So that, components will suffer from higher current and voltage stress. Conduction losses in the converter are more because of the longer conduction of the active switch. Furthermore, the diodes at the output side will conduct very short intervals, resulting in significant reverse recovery issues [4].

In the literature, different types of non-isolated and isolated topologies are available for high voltage boosting [5–7]. By using the coupled inductors, high gain can be achieved. In [8], a soft switched non-isolated three winding coupled inductor type DC/DC converter is presented for high step up renewable energy applications. Here, the three-winding coupled inductor creates more degree of freedom to attain high voltage gain. In renewable energy resources, isolated converters are used for high step-up voltage to overcome higher duty ratio and safety concerns. The isolated topologies like full-bridge, flyback, push-pull, etc., can obtain high voltage gain by changing the transformer’s turns ratio [9–12]. However, the converters in [9, 11] are high gain voltage fed converters (VFC), whereas in [10, 12] are current fed converters (CFC). These converters have some limitations; in the VFC, there is a prohibition with short through of switches in the same leg, to avoid this small dead band is provided in between them. Whereas in CFC, the switches (top & lower) in the same leg triggered together (Shoot through). Otherwise, DC inductor gets opened and it causes high voltage stress on switches and the main circuit gets damaged. VFC are buck type, whereas CFC are boost converters and can’t be used as buck-boost converters. To overcome this, impedance source converters (ISC) are introduced and here switches in the same leg can be short-circuited or open circuited. Hence, the ISC can be operated as buck type, boost type, or both buck-boost types [13–15]. Furthermore, based on topological structure, the ISC can be classified as non-isolated [16–19] and isolated [21–27] type converters. To achieve higher gain a three-winding coupled inductor Y-source converter is proposed in [17], it has more freedom to attain high gain. However, due to the DIC nature of this converter not a good candidate for PV and fuel cell systems. Hence, to overcome this a CIC quasi-Y-source converter is presented in [18]. Furthermore, to reduce the voltage stress on the components and higher voltage gain a modified Y-source DC/DC converter is presented in [19]. Here, all the aforementioned converters are non-isolated, and not suitable for PV, fuel cell systems. Here galvanically isolated impedance source DC/DC converters are present due to safety concerns in PV systems and grid-tied converters.

The first isolated impedance source DC/DC converter was introduced in 2009 [20]. It inherits all the features of the conventional Z-source network. In [21], the reliability and efficiency are improved with a reduced number of switches. However, these converter’s DIC nature is not recommended for PV and fuel cell applications. To resolve this issue, researchers are introduced a CIC isolated quasi-Z source DC/DC converter [22, 23]. Hence, the CIC feature of these converters is mainly preferred for renewable energy resources. Furthermore, magnetically coupled ISC are presented in [24, 25] to improve the gain. The converter in [24], gain is improved by coupled inductor and isolation transformer with reduced switch count. Moreover, due to the DIC nature, this converter is not preferred. In [25], researchers developed a magnetically coupled CIC Y-source DC/DC converter. Moreover, all aforementioned converters are hard switched converters so that turn-on and turn-off losses are more and impact on the overall converter efficiency. Researchers are made efforts to develop soft switching in impedance source DC/DC converters [26–28]. However, the converters in [26, 27] are soft switched and high gain these are not preferred due to non-isolated type. In [28] soft switched, isolated high gain ISC is presented with computerized simulation.

This paper’s main objective is to design high efficieny, compact size, low voltage stress on semiconductor devices and higher power density DC/DC converter to interface renewable energy resources. In the literature, the soft switched frequency modulated high gain DC/DC impedance source converters are not extensively investigated. In this paper, authors are made efforts to develop soft switched frequency modulated impedance source DC/DC converters. To obtained higher gain a magnetically coupled three winding coupled inductor and high frequency transformer is used. Here, output voltage is regulated by varying the switching frequency. Furthermore, soft switching (ZCS) is obtained by properly selecting LC tank, which causes the partial resonance during shoot through instant, and all the active devices (MOSFETs) are turned off with ZCS. There are no additional magnetic components, active and passive devices are used for achieving soft switching (ZCS). This improves the overall efficiency of the converter. Since converter having soft switching feature high frequency operation is possible. Hence magnetic component and other filter capacitor size can be reduced which enhance the power density. Also due to ZCS, the turn off voltage spikes on switches (which is typical problem in current fed converters) are eliminated. This converter inherits all the features of ISC, and it overcome the demerits of a conventional converter [13]. In Section 2 steady state operation and description of the proposed converter is discussed. The design analysis, simulation and experimental results are presented in Sections 3 and 4.

Figure 1 Proposed isolated quasi-Y source DC/DC converter.

2 Discerption and Operation of the Proposed Converter

In Figure 1, the proposed isolated quasi-Y source DC/DC converter is shown. This converter consists of three winding coupled inductors (L$1_{}$, L$2_{}$, and L$3_{}$) having N$1_{}$, N$2_{}$, and N$3_{}$ number of turns in the respective windings, two capacitors C${\mathrm{y1}}_{}$, C${\mathrm{y2}}_{}$, input inductor L${\mathrm{in}}_{}$ and diode D${\mathrm{y}}_{}$. The two DC blocking capacitors C${\mathrm{y1}}_{}$ and C${\mathrm{y2}}_{}$ are used to prevent core saturation in the Y-source coupled inductor. The input inductor is connected in series with the voltage source, and the blocking diode D${\mathrm{y}}_{}$ is connected between the drain of the active switch and the negative terminal of the capacitor C${\mathrm{y2}}_{}$. The output of the quasi-Y source converter is connected to the bridge inverter. The primary and secondary sides of the isolated high-frequency transformer (HFT) are connected to the inverter and rectifier bridges. Here, the LC tank is formed by utilizing the transformer’s parasitic like leakage inductance (L${\mathrm{k1}}_{}$) and winding capacitor (C${\mathrm{p}}_{}$ parasitic capacitor). However, partial resonance is obtained by proper selection of LC tank. This allows all switches in the inverter will turn off with ZCS. The output voltage is controlled using the frequency modulation technique while maintaining the shoot-through duty ratio (d${\mathrm{ST}}_{}$) constant. Here, to utilize the CIC and extensive features of the impedance network presented in [18] is taken. Moreover, the converter in [18] is a non-isolated, PWM-controlled, and hard switched converter. Here, efforts are made to develop a soft switched isolated and frequency modulated high gain converter for renewable energy applications.

2.1 Configuration of Quasi-Y Source Topology [18]

Figure 2(a) presents the equivalent circuit of the CIC quasi-Y source converter. It has three coupled inductors (L$1_{}$, L$2_{}$, and L$3_{}$), one input inductor L${\mathrm{in}}_{}$, one blocking diode D${\mathrm{y}}_{}$, two dc capacitors C${\mathrm{y1}}_{}$, C${\mathrm{y2}}_{}$, and one active switch S${\mathrm{sw}}_{}$. Here, L${\mathrm{m}}_{}$ is the magnetizing inductance of the Y-source coupled inductor with respect to winding one, and V${\mathrm{L}}_{}$ is the voltage across this winding 1. N$1_{}$, N$2_{}$, and N$3_{}$ are the number of turns in each winding. From Figure 2(b), (c), this converter mainly operates in shoot-through and non-shoot through states respectively.

The shoot-through state is depicted in Figure 2(b), in this state, active switch S${\mathrm{sw}}_{}$ is conducting, and diode D${\mathrm{y}}_{}$ is OFF. During this state, input inductor L${\mathrm{in}}_{}$ and magnetizing inductor L${\mathrm{m}}_{}$ are charged. By analysing the circuit, the steady-state analysis can obtain as follows.

$$-V_{C_{y1}}-n_{21}{V}_L+n_{31}{V}_L=0;V_L=\frac{V_{C_{y1}}}{(n_{31}-n_{21})}$$	(1)
$$-V_{in}+V_{L_{in}}-V_{C_{y2}}+V_L+n_{21}{V}_L+V_{C_{y1}}=0$$
$$V_{L_{in}}=V_{in}+V_{C_{y2}}-V_{C_{y1}}-(1+n_{21})V_L$$	(2)

Figure 2 Equivalent circuit (a) CIC quasi-Y source converter, (b) Shoot through state, (c) Non-shoot through state.

Non-shoot through state is presented in Figure 2(c). During this state, switch S${\mathrm{sw}}_{}$ is OFF, and diode D${\mathrm{y}}_{}$ is conducting. By analysing the circuit, the following expressions are obtained.

$$V_{C_{y2}}-n_{31}{V}_L-V_L=0;V_L=\frac{V_{C_{y2}}}{(n_{31}+1)}$$	(3)
$$-V_{in}+V_{L_{in}}-V_{C_{y2}}+V_L+n_{21}{V}_L+V_{C_{y1}}=0$$
$$V_{L_{in}}=V_{in}+V_{C_{y2}}-V_{C_{y1}}-(1+n_{21})V_L$$	(4)
$$-V_{in}+V_{L_{in}}+V_i=0;V_i=V_{in}-V_{L_{in}}$$	(5)
$$V_i=V_{C_{y1}}-V_{C_{y2}}+(1+n_{21})V_L$$	(6)

Here, $n_{21}=\frac{N_2}{N_1}$, $n_{31}=\frac{N_3}{N_1}$ are turns ratios of N$1_{}$, N$2_{}$, N$3_{}$ and $V_i$ is the DC link voltage.

By state-space averaging, from (1) and (3) the resultant can obtain as follows.

$$\frac{V_{C_{y1}}}{(n_{31}-n_{21})}{d}_{ST}+\frac{V_{C_{y2}}}{(n_{31}+1)}(1-d_{ST})=0$$
$$\frac{V_{C_{y2}}}{V_{C_{y1}}}=\frac{(n_{31}+1)d_{ST}}{(n_{31}-n_{21})(1-d_{ST})}$$	(7)

Applying state-space averaging at input inductor L${\mathrm{in}}_{}$, by using (2), (4) and after solving the below equation, we will obtain (8).

$\mathrm{\{}{V}_{in}+V_{C_{y2}}-V_{C_{y1}}-(1+n_{21})V_L\}d{ST}_{}$
$\mathrm{\hspace{1em}\hspace{1em}}+\{V_{in}+V_{C_{y2}}-V_{C_{y1}}-(1+n_{21})V_L\}(1-d_{ST})=0;$
$V_{C_{y2}}=V_{C_{y1}}-V_{in}$	(8)

By using (7) and (8), the simplified individual capacitor voltages are obtained as

$V_{C_{y1}}$	$={\displaystyle \frac{(1-d_{ST})V_{in}}{1-\left(\frac{n_{21}+1}{n_{21}-n_{31}}\right)d_{ST}}}$	(9)
$V_{C_{y2}}$	$={\displaystyle \frac{\left(\frac{n_{31}+1}{n_{21}-n_{31}}\right)d_{ST}{V}_{in}}{1-\left(\frac{n_{21}+1}{n_{21}-n_{31}}\right)d_{ST}}}$	(10)

By substituting (3), (9), and (10) in (6), the resultant DC link voltage can be obtained as follows.

$$V_i=\frac{1}{1-\left(\frac{1+n_{21}}{n_{21}-n_{31}}\right)d_{ST}}{V}_{in}=\frac{1}{(1-\delta d_{ST})}{V}_{in}$$

(11)

Here, $\delta$ is the winding factor of quasi-Y source coupled inductor.

$$\delta =\frac{1+n_{21}}{n_{21}-n_{31}}=\frac{N_1+N_2}{N_2-N_3},\text{and}\mathit{\hspace{1em}}{n}_{21}=\frac{N_2}{N_1},n_{31}=\frac{N_3}{N_1}.$$

(12)

For each selected value of $\delta$, various combinations of turns ratios N$1_{}$: N$2_{}$: N$3_{}$ are realized, illustrated in the Table 1.

From Equation (11), the allowable shoot through duty variation is given as follows

$$0\le d_{ST}\le d_{\mathit{ST},\mathit{max}}=\frac{1}{\delta }$$

(13)

The relation of d${\mathit{ST}}_{}$ and conventional duty (D) is given as below.

$$d_{\mathit{ST}}=2D-1$$

(14)

Table 1 Realization of Shoot-through duty ratio (d${\mathrm{ST}}_{}$) and winding factor ($\delta$) with different turns ratios (N$1_{}$: N$2_{}$: N$3_{}$)

$\delta ={\displaystyle \frac{N_1+N_2}{N_2-N_3}}$	$d_{ST,max}$	Conventional Duty Range (D)	(N${\mathrm{1}}_{}$: N${\mathrm{2}}_{}$: N${\mathrm{3}}_{}$) Turns Ratio
2	1/2	0.5 $\le$ D $\le$ 3/4	(1:3:1), (2:4:1), (3:5:1)
3	1/3	0.5 $\le$ D $\le$ 4/6	(1:4:1), (3:3:1), (2:4:2)
4	1/4	0.5 $\le$ D $\le$ 5/8	(2:2:1), (1:3:2), (5:3:1)
5	1/5	0.5 $\le$ D $\le$ 6/10	(3:2:1), (2:3:2), (1:4:3)
6	1/6	0.5 $\le$ D $\le$ 7/12	(4:2:1), (3:3:2), (2:4:3)
7	1/7	0.5 $\le$ D $\le$ 8/14	(4:3:2), (5:2:1), (3:4:3)
8	1/8	0.5 $\le$ D $\le$ 9/16	(5:3:2), (6:2:1), (3:5:4)

2.2 Steady State Analysis and Modes of Operation of the Proposed Converter

The steady-state waveform of the proposed converter is presented in Figure 3. Here, by utilizing the transformer’s parasitic L${\mathrm{k1}}_{}$ and C${\mathrm{p}}_{}$, soft switching (ZCS) is achieved at the turn-off instant. To regulate the output voltage, here frequency modulation technique is implemented. Here constant shoot through duty (d${\mathrm{ST}}_{}$) is chosen for soft computation of power MOSFETs. The gate signals, pair of V${\mathrm{GS1}}_{}$, V${\mathrm{GS3}}_{}$, and pair of V${\mathrm{GS2}}_{}$, V${\mathrm{GS4}}_{}$ is 180${\circ }^{}$ phase-modulated each other with small D${\mathrm{ST}}_{}$. The converter analysis is studied for the first half cycle over five operating modes with detailed discussion is given. The equivalent circuit operation is depicted in Figure 4.

Figure 3 The steady-state waveforms of the quasi-Y source DC/DC impedance converter.

Figure 4 Operating modes of proposed topology (a) Mode I, (b) Mode II, (c) Mode III, (d) Mode IV, (e) Mode V.

Mode I: ${\mathit{\text{t}}}_{\mathbf{\text{1}}}\sim {\mathit{\text{t}}}_{\mathbf{\text{2}}}$ [Figure 4(a)]

This mode is started at t$1_{}$. Before that, power MOSFETs S$2_{}$, S$4_{}$ are in conduction, and energy is transferred from source to load. At t $=$ t$1_{}$, the MOSFET pairs S$1_{}$ and S$3_{}$ are triggered, and all the MOSFETs are under conduction. In a bridge rectifier, D$2_{}$ and D$4_{}$ are conducting, and D$1_{}$ and D$3_{}$ are off. The diode D${\mathrm{y}}_{}$ in the impedance network is also off. Here, the leakage inductor L${\mathrm{k1}}_{}$ and input inductor L${\mathrm{in}}_{}$ starts charging. The current flows through L${\mathrm{k1}}_{}$ and L${\mathrm{in}}_{}$ linearly increases. The current through the power MOSFETs S$1_{}$, S$3_{}$ increases, whereas in S$2_{}$, S$4_{}$ are decreased, and these can be observed in Figure 3. The voltage across C${\mathrm{p}}_{}$ and current through L${\mathrm{k1}}_{}$ is given as follows.

$$V_{C_p}(t)=-\frac{1}{n}{V}_O$$	(15)
$$i_{L_{k1}}(t)=\frac{V_O}{n{L}_{k1}}(t-t_1)-I_i$$	(16)

Time duration for this Mode I is obtained as follows

$$T_{21}=t_2-t_1=\frac{n{I}_i{L}_{K1}}{V_O}$$

(17)

Here n is the turns ratio of HFT, and this mode ends at t$2_{}$ when L${\mathrm{k1}}_{}$ current reaches zero.

Mode II: ${\mathit{\text{t}}}_{\mathbf{\text{2}}}\sim {\mathit{\text{t}}}_{\mathbf{\text{3}}}$ [Figure 4(b)]

This mode will start at t$2_{}$, when diodes D$2_{}$, D$4_{}$ in the bridge rectifier are reverse biased. All the power MOSFETs are conducting, and D${\mathrm{y}}_{}$ is off. The transformer’s parasitic L${\mathrm{k1}}_{}$ and C${\mathrm{p}}_{}$ form the LC tank cause resonance in the circuit. The current through switch pairs S$1_{}$ and S$3_{}$ is still increasing, and the switch pairs S$2_{}$ and S$4_{}$ are decreasing.

The current through L${\mathrm{k1}}_{}$ is given as

$$i_{L_{k1}}(t)=\frac{V_O}{n{Z}_r}\sin (w_r(t-t_2))$$	(18)
$$w_r=2\pi f_r,f_r=\frac{1}{2\pi \sqrt{L_{k1}{C}_p}}$$	(19)
$$Z_{cr}=\sqrt{\frac{L_{k1}}{C_p}}$$	(20)

Here, z${\mathrm{cr}}_{}$, f${\mathrm{r}}_{}$, and w${\mathrm{r}}_{}$ are characteristic impedance of the network, resonant frequency, and angular frequency respectively. The time duration for this mode is given in (21)

$$T_{32}=t_3-t_2=\frac{1}{W_r}{\sin }^{-1}\left(\frac{n{I}_i{Z}_{cr}}{V_O}\right),\mathrm{\hspace{0.25em}0}<w_r{T}_{32}<\frac{\pi }{2}$$

(21)

Mode III: ${\mathit{\text{t}}}_{\mathbf{\text{3}}}\sim {\mathit{\text{t}}}_{\mathbf{\text{4}}}$ [Figure 4(c)]

This mode will start at t$3_{}$ when the value of leakage inductor current $i_{L_{k1}}$ is equal to I${\mathrm{i}}_{}$. At this instant, the current through the power MOSFETs S$2_{}$, S$4_{}$ is zero and which are turned off with ZCS. Currently, the conducting devices are S$1_{}$, S$3_{}$, body diodes of S$2_{}$, S$4_{}$, and D${\mathrm{y}}_{}$. The current through L${\mathrm{k1}}_{}$ reaches the peak value I${\mathrm{pk}}_{}$ at t $=$ t${}^{\prime }3$, whereas voltage across the C${\mathrm{p}}_{}$ is zero.

$$I_{Pk}=\frac{V_O}{n{Z}_{cr}}\ge I_i$$

(22)

Here I${\mathrm{pk}}_{}$ is the peak value of L${\mathrm{k1}}_{}$ current, and the time duration ($t_4-t_2$) is given by

$$T_{42}=\frac{\pi -w_r{T}_{32}}{w_r}$$

(23)

Mode IV: ${\mathit{\text{t}}}_{\mathbf{\text{4}}}\sim {\mathit{\text{t}}}_{\mathbf{\text{5}}}$ [Figure 4(d)]

At t $=$ t$4_{}$, when the L${\mathrm{k1}}_{}$ current $(i_{L_{k1}})$ reaches to $I_i$ this mode will start. This instant body diodes of S$2_{}$, S$4_{}$ turned off, and the power MOSFETs S$1_{}$, S$3_{}$, diode D${\mathrm{y}}_{}$ are still conducting. Here at the end of this mode parasitic capacitor C${\mathrm{p}}_{}$ is fully charged with I${\mathrm{i}}_{}$ current. The time taken for this mode is given as follows

$$T_{54}=t_5-t_4=\frac{V_O(1+\cos (w_r(t_4-t_2)))C_P}{n{I}_i}$$

(24)

Mode V: ${\mathit{\text{t}}}_{\mathbf{\text{5}}}\sim {\mathit{\text{t}}}_{\mathbf{\text{6}}}$ [Figure 4(e)]

During this mode, C${\mathrm{p}}_{}$ is fully charged with voltage of V${\mathrm{i}}_{}$ and the diodes D$1_{}$, D$3_{}$ in rectifier bridge start conducting. Here, the power MOSFETs S$1_{}$, S$3_{}$ and D${\mathrm{y}}_{}$ are in conduction. Here energy is transferring to the load and leakage inductor current $i_{L_{K1}}(t)$ is equal to the $I_i$.

$$i_{L_{K1}}(t)=I_i$$

(25)

The time duration for half switching period (T${\mathrm{s}}_{}$/2) is equal to total time duration of Mode I to V, and it is given as follows

$$t_6-t_1=\frac{1}{2}{T}_s$$

(26)

3 Design Analysis of the Quasi-Y Source Converter

In the CIC quasi-Y source converter, the coupled inductor is represented by a three-winding ideal transformer with leakage inductance and magnetizing inductance of each winding. Here all the power MOSFETs and diodes are ideal.

3.1 Voltage Gain (M)

The average output current ($I_{R_o}$) is given as

$$I_{R_o}=\frac{V_o}{R_o}=\frac{I_{L_{k1,\mathit{avg}}}}{n}=\frac{2}{n{T}_s}{\int }_0^{\frac{T_s}{2}}{I}_{L_{k1}}(t)\mathit{d}t$$

(27)

From the power balance equation

$$P_o=\frac{V_o^2}{R_o}=V_{in}{I}_{in}=V_i{I}_i$$	(28)
$$I_i=\frac{V_o^2}{V_i{R}_o}$$	(29)

Here is the efficiency of the converter, n is the turns ratio of the HFT, and R${\mathrm{o}}_{}$ is the full load resistance.

By using (26), (27), and (29), the voltage at the output side is obtained as

$$V_o=\frac{n{V}_i}{1-2f_s\left(\frac{1}{2}{T}_{21}+T_{42}+T_{54}\right)}$$

(30)

The output voltage can be obtained by substituting the Equations (17), (23), and (25) in (30). Hence it is derived as follows.

$$V_o=\frac{n{V}_i}{1-f_n\left(1+\frac{x}{2\pi }-\frac{1}{\pi }{\sin }^{-1}x+\frac{1}{\pi }\frac{(1-\sqrt{1-x^2})}{x}\right)}$$

(31)

The proposed converter gain is obtained as

$$M=\frac{V_o}{V_{in}}=\frac{V_o}{V_i}*\frac{V_i}{V_{in}}$$

(32)

By using (11), (31), and (32) the resultant gain of the proposed converter is obtained as

$$M=\frac{V_o}{V_{in}}=\frac{n}{1-f_n\left(1+\frac{x}{2\pi }-\frac{1}{\pi }{\sin }^{-1}x+\frac{1}{\pi }\frac{\left(1-\sqrt{1-x^2}\right)}{x}\right)}\times \frac{1}{(1-\delta d_{ST})}$$

(33)

Here, $f_n=\frac{f_s}{f_r}$, $x=\frac{M}{n{r}_n}$, $r_n=\frac{1}{n^2}\times \frac{R_o}{z_r}$, f${\mathrm{n}}_{}$ $=$ Normalized frequency, f${\mathrm{s}}_{}$ $=$ Switching frequency, f${\mathrm{r}}_{}$ $=$ Resonant frequency, M $=$ Gain of the converter, r${\mathrm{n}}_{}$ $=$ Normalized resistance, R${\mathrm{o}}_{}$ $=$ Full load output resistance, Z${\mathrm{r}}_{}$=Characteristic impedance. The gain of the converter for the ideal case depends on the turns ratio of the transformer (n), winding factor (12), and shoot through duty (d${\mathrm{ST}}_{}$). The gain of the proposed converter is shown in Figure 5 at different turns ratio of the transformer. The converter gain is increased by increasing the turns ratio of the transformer.

Figure 5 Gain curve with normalized frequency (f${\mathrm{n}}_{}$).

3.2 Design of Input Inductor

The input inductor can be designed based on the current ripple. The current ripple at the input inductor is given as

$$\mathrm{\Delta }{I}_{L_{in}}={\int }_{d_{ST}{T}_s}^{T_s}\frac{d{i}_{L_{in}}}{dt}\mathit{d}t={\int }_{d_{ST}{T}_s}^{T_s}\frac{V_{L_{in}}}{L_{in}}\mathit{d}t=\frac{V_{L_{in}}}{L_{in}}(1-d_{ST})T_s$$

(34)

From Equation (5)

$$V_{L_{in}}=V_{in}-V_i$$	(35)
$$L_{in}=\frac{(V_{in}-V_i)(1-d_{ST})}{\mathrm{\Delta }{I}_{L_{in}}{f}_s}$$	(36)

3.3 Condition for ZCS

Here the LC tank must be designed properly to obtain ZCS. The L${\mathrm{k1}}_{}$ and C${\mathrm{p}}_{}$ stored energy is mainly responsible for achieving soft switching, and selected value Z${\mathrm{cr}}_{}$ should satisfy the following condition.

$$Z_{cr}<\frac{V_0}{n{I}_{i,\mathit{max}}}=\frac{V_{\mathit{in},\mathit{min}}{R}_o}{n{V}_O}$$

(37)

3.4 ${\mathit{L}}_{\mathit{k}\mathbf{1}}$ and ${\mathit{C}}_{\mathit{p}}$ Design

The transformer parasitic’s L${\mathrm{k1}}_{}$ and C${\mathrm{p}}_{}$ must be chosen carefully to accomplish ZCS. The characteristic impedance (Z${\mathrm{cr}}_{}$) is obtained from Equation (37). By utilizing Equations (20) and (37), the L${\mathrm{k1}}_{}$, C${\mathrm{p}}_{}$ parameters are calculated. The selected value of Z${\mathrm{cr}}_{}$ should satisfy the ZCS condition (37).

3.5 Voltage Stress of MOSFETs and Diodes

The voltage stress on MOSFETs and output diodes is given in (37), (38). From (37), the voltage stress on all MOSFETs is dependent on the output voltage and the number of turns in the HFT. The diodes voltage stress is the same as the output voltage.

$$V_{S_{1-4}}=\frac{V_o}{n}=V_i$$	(38)
$$V_{D_{1-4}}=V_o$$	(39)

4 Discussion on Simulation/Hardware Results

The performance of a quasi-Y source high gain DC/DC resonant converter using PSIM Simulink, and hardware prototype is presented. Here, the converter is designed for 300 W power and, the input voltage varies (40–60) V and output is regulated to standard 380 V DC grid voltage. Here output voltage is regulated by varying switching frequency at constant shoot through duty (d${\mathrm{ST}}_{}$). The switching frequency is varied from 85 kHz to 190 kHz. When the input voltage is 40 V, to regulate the rated output voltage converter is operated at 190 kHz and when input voltage is 60 V to regulate the rated output an 85 kHz switching frequency is applied. In Table 2, the converter specifications and other design parameters are given.

Table 2 Components and parameters specifications

Parameter	Specification Value
Rated Power (P${\mathrm{o}}_{}$)	300 W
Input voltage (V${\mathrm{in}}_{}$)	40–60 V
Output voltage (V${\mathrm{o}}_{}$)	380 V
Switching frequency (f${\mathrm{s}}_{}$)	85–190 kHz
Shoot through duty (d${\mathrm{ST}}_{}$)	0.15
Input inductor (L${\mathrm{in}}_{}$)	2 mH
Capacitors	C${}_{\mathrm{y1}}=68\mu$F, C${}_{\mathrm{y2}}=22\mu$F, C${}_{\mathrm{o}}=200\mu$F
Power MOSFETs	IRFP4227pbf, R${}_{\mathrm{DS}(\mathrm{on})}=21$ m$\mathrm{\Omega }$
Diodes	RHRG75120
Coupled Inductor (N$1_{}$: N$2_{}$: N$3_{}$)	EE55/28/21 Ferrite core (16:16:8)
Winding Factor ($\delta$)	4
HFT (N$1_{}$: N$2_{}$)	EE42/21/15 Ferrite core (4: 20)
L${\mathrm{k1}}_{}$	0.85 $\mu$H
C${\mathrm{p}}_{}$	0.18 $\mu$F

Figure 6 Experimental prototype of Quasi-Y source DC/DC converter.

The experimental photograph of the converter is shown in Figure 6. The coupled inductor is designed using EE55 gapped ferrite core with a 16:16:8 number of turns. All the windings are wound tightly in Y shape manner. EE42 ferrite core is used for HFT. Hence, the tight coupling of the inductor and transformer results in less parasitic resistance and leakage in each winding. Moreover, to reduce the skin effect and ac resistance of winding Litz wires are used. For generating gate signals, (TMS320F28335) TI supported C2000 development kit is used. All the active and passive components are selected to achieve lower losses.

The simulation and experimental tests are performed at rated power of 300 W with 48 V input voltage. The output voltage is regulated to 380 V by varying the switching frequency up to 150 kHz. The switching pulses of the proposed topology with small shoot-through duty (d${}_{\mathrm{ST}}=0.15$) presented in a dotted circle and operating at 150kHz switching frequency are shown in Figure 7. Here, the gate pulse of MOSFETs 1, 3, and MOSFETs 2, 4 are modulated with a 180${\circ }^{}$ phase difference.

The key waveforms of simulation results are shown in Figures 8(a), 9(a), 10(a), 11(a), respectively. The developed prototype experimental results are shown in Figures 8(b), 9(b), 10(b), 11(b). Here, the simulation and experimental test are done at the rated condition of the developed converter. Both simulated and experimental results are found to be identical.

Figure 7 Gate pulse of the proposed converter at switching frequency f${}_{\mathrm{s}}=150$ kHz.

Figure 8 Standard waveforms obtained from (a) simulation and (b) Experimental results of gate signals, voltage stress, current through the pair of switches S$1_{}$, S$3_{}$ at rated condition.

Figure 9 Standard waveforms obtained from (a) simulation and (b) Experimental results of gate signals, voltage stress, current through the pair of switches S$2_{}$, S$4_{}$ at rated condition.

Figure 8 shows simulation and hardware results of gate signal (V${\mathrm{gs1}}_{}$, V${\mathrm{gs3}}_{}$), voltage stress (V${\mathrm{ds1}}_{}$, V${\mathrm{ds3}}_{}$), and currents (I${\mathrm{S1}}_{}$, I${\mathrm{S3}}_{}$) through the active switch pairs S$1_{}$, S$3_{}$. The simulation and experimental results of gate signal (V${\mathrm{gs2}}_{}$, V${\mathrm{gs4}}_{}$), voltage stress (V${\mathrm{ds2}}_{}$, V${\mathrm{ds4}}_{}$), and currents (I${\mathrm{S2}}_{}$, I${\mathrm{S4}}_{}$) through the switch pairs S$2_{}$, S$4_{}$ are depicted in Figure 9. It is observed from Figures 8, 9 all the switches S$1_{}$ to S$4_{}$ are turned off with ZCS and denoted in a dotted circle. It helps the converter can operate at a higher frequency with lower switching losses. The voltage of the switches is settled at 120 V, and the peak current reaches 20 A during the shoot-through instant.

Figure 10 Standard waveforms obtained from (a) simulation and (b) Experimental results of diode voltage (V${\mathrm{D1}}_{}$, V${\mathrm{D3}}_{}$), inverter output (V${\mathrm{ab}}_{}$), output voltage (V${\mathrm{o}}_{}$) at rated condition.

Figure 11 Standard waveforms obtained from (a) simulation and (b) Experimental results of parasitic capacitor voltage (V${\mathrm{Cp}}_{}$), inverter output voltage (V${\mathrm{ab}}_{}$), Current through Leakage inductor (I${\mathrm{Lk1}}_{}$) at rated condition.

Figure 10 shows the simulation and experimental results of voltage stress on rectifier diodes (V${\mathrm{D1}}_{}$, V${\mathrm{D3}}_{}$), output of inverter bridge voltage (V${\mathrm{AB}}_{}$) and output voltage (V${\mathrm{o}}_{}$). The simulation and experimental results have observed that peak value of diode and output voltage is settled at 380 V. At the same time, the inverter output voltage (V${\mathrm{AB}}_{}$) is settled at 120 V. In Figure 11, the voltage across the parasitic capacitor (V${\mathrm{Cp}}_{}$), the output of inverter bridge voltage (V${\mathrm{AB}}_{}$) and current through the leakage inductor (I${\mathrm{Lk1}}_{}$) are shown. The simulation and experimental results were observed that parasitic and inverter bridge voltage is settled at 120 V. When I${\mathrm{Lk1}}_{}$ reaches a peak value of 36 A, the same instant V${\mathrm{Cp}}_{}$ voltage is zero.

The individual losses in each element are computed by using loss equations given in Table 3 and the parameters of selected components in the datasheet. The efficiency of the converter is obtained by using Equation (40) and associated total losses in the converter. Here, some of the efficiency model calculations are tabulated in Table 4.

$$\mathit{Efficiency}()=\frac{P_o}{P_o+\mathit{losses}}\times 100$$

(40)

Table 3 Losses equations used to compute losses in the converter

Description	Equation
Gate driver losses	$C_{iss}\times V_g^2\times f_{sw}$
Capacitor losses	$I_{Co,rms}^2\times R_{ESR}$
Switch conduction losses	$I_{sw,rms}^2\times R_{DS(on)}$
Turn on losses in the switch	$\frac{1}{2}{C}_{oss}\times V_{sw}^2\times f_{sw}$
Total losses in rectifier diodes	$V_{Df}{I}_{D,avg}+I_{D,rms}^2{R}_D+V_d{Q}_{rr}{f}_{sw}$
Total losses in the HFT	$I_{t,rms}^2{R}_{winding}+P_{climit}{V}_e$
Total losses in the inductor	$I_{L,rms}^2{R}_{L,DC}+P_{climit}{V}_e$

Table 4 Efficiency calculations of proposed converter

Input Voltage	Parameter	50 W	150 W	300 W
40 V	Po	47.425	145.642	290.92
	Losses	1.513	4.137	9.104
	Efficiency	96.9	97.23	96.96
48V	Po	47.613	147.243	291.83
	Losses	1.271	3.112	7.021
	Efficiency	97.39	97.93	97.65
60V	Po	48.512	147.431	292.967
	Losses	1.005	2.425	6.192
	Efficiency	97.97	98.38	97.93

Were

C${\mathrm{iss}}_{}$ $=$ Switch input capacitor (F)

V${\mathrm{g}}_{}$ $=$ Switch driving voltage (V)

f${\mathrm{sw}}_{}$ $=$ Switching frequency (Hz)

I${\mathrm{Co},\mathrm{rms}}_{}$ $=$ Capacitor rms ripple current (A)

R${\mathrm{ESR}}_{}$ $=$ Capacitor equivalent series resistor ($\mathrm{\Omega }$)

I${\mathrm{sw},\mathrm{rms}}_{}$ $=$ Switch rms current (A)

R${\mathrm{DS}(\mathrm{on})}_{}$ $=$ Switch drain to source on-state resistance ($\mathrm{\Omega }$)

C${\mathrm{oss}}_{}$ $=$ Switch output capacitor (F)

V${\mathrm{sw}}_{}$ $=$ Switch average voltage at turn off time (V)

V${\mathrm{Df}}_{}$ $=$ Diode forward voltage (V)

I${\mathrm{D},\mathrm{rms}}_{}$ $=$ Diode rms current (A)

I${\mathrm{D},\mathrm{avg}}_{}$ $=$ Diode average current (A)

R${\mathrm{D}}_{}$ $=$ Diode turn on resistance ($\mathrm{\Omega }$)

V${\mathrm{d}}_{}$ $=$ Diode blocking voltage (V)

Q${\mathrm{rr}}_{}$ $=$ Diode reverse recovery charge

I${\mathrm{t},\mathrm{rms}}_{}$ $=$ rms current through transformer (A)

R${\mathrm{winding}}_{}$ $=$ Transformer DC resistance ($\mathrm{\Omega }$)

P${\mathrm{C}\mathrm{limit}}_{}$ $=$ Core loss limit (mW/cm$3^{}$)

V${\mathrm{e}}_{}$ $=$ Effective core volume (cm$3^{}$)

I${\mathrm{t},\mathrm{rms}}_{}$ $=$ rms current through transformer (A)

Figure 12 Efficiency of the proposed converter.

At 60 V rated power (300 W) the calculated efficiency of the converter is given below.

$\mathit{Efficiency}()$	$={\displaystyle \frac{P_o}{P_o+\mathit{losses}}}\times 100$
	$={\displaystyle \frac{292.967}{292.967+6.192}}\times 100=97.93\%$

The mathematical efficiency calculation of converter is given in Table 4. The maximum efficiency of 98.38% is obtained for 60 V input at 150 W power. Minimum efficiency of 96.90% for 40 V input with 50 W power. In Figure 12 the measured efficiency of the converter is given. Here, the experimental efficiency values are slightly lesser then the mathematically calculated one. But both are very close, and the slight variation is due to the change in the resistance of the semiconductor while operating temperature changes.

5 Conclusion

A quasi-Y source magnetically coupled isolated partial resonant DC/DC converter is presented. By utilizing HFT parasitic components, LC parallel tank is formed, and soft switching (ZCS) occurs during the MOSFET turn-off instant. The mathematical and design methodology of the proposed converter is discussed. In addition, the simulation and experimental results are used to analyze the performance of the converter. Furthermore, coupled inductor and HFT provide a high voltage gain with less voltage stress on MOSFETs. Furthermore, it brings merits of ISC, and the soft switching feature improves the converter efficiency up to 98.38% at 60 V input voltage. The high gain, galvanic isolation and CIC feature of this converter are most suitable for renewable energy applications.

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Biographies

Sugali Harinaik, received the B.Tech. degree in electrical and electronics engineering from the JNTUA College of Engineering Pulivendula, Andhrapradesh, India, in 2013 and the M.Tech. degree in integrated power systems from Visvesvaraya National Institute of Technology Nagpur, India, in 2017. He is currently working toward the Ph.D. degree in electrical and electronics engineering at National Institute of Technology, Tiruchirappalli, India.

His research interests include high gain DC/DC converters for renewable energy sources, soft switching, and impedance source DC/DC converters.

Shelas Sathyan, received the B.Tech. degree in electrical and electronics engineering from the Government College of Engineering Kannur, India, in 2009, and the M.Tech. and Ph.D. degrees in electrical engineering from the Visvesvaraya National Institute of Technology, Nagpur, India, in 2012 and 2017, respectively.

He is currently an Assistant Professor with the Department of electrical and electronics engineering at National Institute of Technology, Tiruchirappalli, India. His research interests include dc/dc converters, soft switching, DAB converters, and power factor correction.

Distributed Generation & Alternative Energy Journal, Vol. 38_2, 569–594.
doi: 10.13052/dgaej2156-3306.3829
© 2023 River Publishers

Abstract

1 Introduction

2 Discerption and Operation of the Proposed Converter

2.1 Configuration of Quasi-Y Source Topology [18]

2.2 Steady State Analysis and Modes of Operation of the Proposed Converter

Mode I: ${\mathit{\text{t}}}_{\mathbf{\text{1}}}\sim {\mathit{\text{t}}}_{\mathbf{\text{2}}}$ [Figure 4(a)]

Mode II: ${\mathit{\text{t}}}_{\mathbf{\text{2}}}\sim {\mathit{\text{t}}}_{\mathbf{\text{3}}}$ [Figure 4(b)]

Mode III: ${\mathit{\text{t}}}_{\mathbf{\text{3}}}\sim {\mathit{\text{t}}}_{\mathbf{\text{4}}}$ [Figure 4(c)]

Mode IV: ${\mathit{\text{t}}}_{\mathbf{\text{4}}}\sim {\mathit{\text{t}}}_{\mathbf{\text{5}}}$ [Figure 4(d)]

Mode V: ${\mathit{\text{t}}}_{\mathbf{\text{5}}}\sim {\mathit{\text{t}}}_{\mathbf{\text{6}}}$ [Figure 4(e)]

3 Design Analysis of the Quasi-Y Source Converter

3.1 Voltage Gain (M)

3.2 Design of Input Inductor

3.3 Condition for ZCS

3.4 ${\mathit{L}}_{\mathit{k}\mathbf{1}}$ and ${\mathit{C}}_{\mathit{p}}$ Design

3.5 Voltage Stress of MOSFETs and Diodes

4 Discussion on Simulation/Hardware Results

5 Conclusion

References

Biographies