Crosstalk Reduction on Delay Line with Rectangular-Patches (RPs) Design

Authors

  • Ding-Bing Lin Department of Electronic and Computer Engineering National Taiwan University of Science and Technology, Taipei, Taiwan
  • Ariana Tulus Purnomo Department of Electronic and Computer Engineering National Taiwan University of Science and Technology, Taipei, Taiwan
  • Chung-Pin Huang Advanced Development Department WIESON Technologies Co., LTD., New Taipei, Taiwan

Keywords:

Far-End Crosstalk (FEXT), helix delay lines, Rectangular-Patches (RPs), Signal Integrity (SI)

Abstract

In this paper, a novel helix delay line with RPs structures is proposed to investigate the performance of crosstalk reduction. In the past, conventional delay lines consist of equal-length parallel unit lines which are closely packed to minimize the fabricated cost and routing area. All spacing between the adjacent parallel unit lines of delay lines should be smaller. When the operating signal frequency ups to the GHz level, the electromagnetic noise has become a dominant issue coupling from adjacent lines. It is called as a crosstalk source. The crosstalk may affect system-level timing. Besides, it causes error switching of logic gates that will reduce the signal quality. The feature of proposed helix delay line is that the far-end crosstalk (FEXT) is a dominated noise that accumulates at the receiving end. RPs structures are added and aligned at the center of the two parallel adjacent unit lines of the proposed helix delay line, which are used to reduce the difference between inductive and capacitive coupling coefficient ratios, and to reduce FEXT that maintains the signal integrity (SI) quality on receiving end.

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Author Biographies

Ding-Bing Lin, Department of Electronic and Computer Engineering National Taiwan University of Science and Technology, Taipei, Taiwan

Ding-Bing Lin received the M.S. and Ph.D. degrees in Electrical Engineering from the National Taiwan University, Taipei, Taiwan, in 1989 and 1993 respectively. From Aug. 1993 to July 2016, he had been on the faculty of the Electronic Engineering Department, National Taipei University of Technology, Taipei, Taiwan, where he was an Associate Professor, a Professor and a Distinguished Professor in 1993, 2005 and 2014 respectively. Since Aug. 2016, he had been with National Taiwan University of Science and Technology, Taipei, Taiwan, where he is currently a Professor of the Electronic and Computer Engineering Department. His current research interests include wireless communication, radio multipath fading channel modeling, mobile antennas, high-speed digital transmission, and microwave engineering. From 2015 to 2018, he served as the Taipei Chapter Chair, IEEE EMC society. Now he serves as Associate Editor of IEEE Transactions of Electromagnetic Compatibility. He also serves on the Editorial Board member of the International Journal of Antennas and Propagation since 2014. So far he has published more than 100 papers in the international journals and conferences.

Ariana Tulus Purnomo, Department of Electronic and Computer Engineering National Taiwan University of Science and Technology, Taipei, Taiwan

Ariana Tulus Purnomo received the B.S. and M.S. degrees in Electrical Engineering from the Institute Technology Bandung (ITB), Bandung, Indonesia, 2015 and 2017 respectively. Besides, she also received her M.E. degree in Interdisciplinary Program of Information System from Pukyong National University (PKNU), Busan, South Korea in 2017. She is currently working toward the Ph.D. degree with the Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology, Taiwan, under the supervision of Dr. Ding-Bing Lin. Her current research interests include wireless communication, radio multipath fading channel modeling, high-speed digital transmission, and microwave engineering.

Chung-Pin Huang, Advanced Development Department WIESON Technologies Co., LTD., New Taipei, Taiwan

Chung-Pin Huang received the M.S. and Ph.D. degrees in Graduate Institute of Computer and Communication Engineering, from the National Taipei University of Technology, Taipei, Taiwan, in 2011 and 2016 respectively. He joined the Cable Assembly Research Department, WIESON Technologies Company, Ltd., Taipei, as an SI Engineer, in 2001, where he was a Manager of the CAE Laboratory from 2004 to 2015 and where he is currently a Chief Technology Officer. His current research interests include signal integrity for high-speed connector, high-speed digital system design, and electromagnetic compatibility for high-speed components.

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Published

2021-01-08

How to Cite

[1]
Ding-Bing Lin, Ariana Tulus Purnomo, and Chung-Pin Huang, “Crosstalk Reduction on Delay Line with Rectangular-Patches (RPs) Design”, ACES Journal, vol. 36, no. 1, pp. 10–19, Jan. 2021.

Issue

2021: Vol 36 Iss 1

Section

General Submission