A Physics-based Transient Simulation and Modeling Method for Wide-frequency Electrical Overstress Including ESD
Keywords:Electric overstress, electrostatic discharge (ESD), transient simulation, wide-frequency
Circuits design that meets various IEC electrical overstress (EOS) standards is still a challenge, for that different kinds of EOS are at different frequency bands. In this paper, a physics-based transient simulation and modeling method is proposed, which can simulate wide-frequency EOS including electrostatic discharge (ESD) and AC characteristics. In this method, the physical model is used to characterize the nonlinear semiconductor devices in the finite-difference timedomain (FDTD)-SPICE co-simulation. Moreover, the modeling and physical parameters extraction method of the ESD protect devices, the transient voltage suppressor diode, is demonstrated. Taking an EOS protection circuit for example, it is modeled and simulated by the proposed method. Moreover, the circuit is also simulated by the widely-used System-Efficient ESD Design (SEED) method, in which the TVS diode is modeled based on 100 ns Transmission Line Pulse (TLP) measurements. The experiments show that both this method and SEED method can characterize the IEC system-level ESD behaviors well. However, the error of the SEED is about 219.2% at 10 MHz AC characteristics, but the maximum error of the proposed method is only 7.8%. Hence, compared with the widely-used SEED method, this method is more accurate when characterizing the EOS event during AC operation and switching.
S. H. Voldman, Electrical Overstress (EOS): Devices, Circuits and Systems. John Wiley & Sons, pp. 1-29, Oct. 2013.
R. Ashton, F. Bahrenberg, J. Dunnihoo, P. Design, and C. Duvvury, “White Paper 4 Understanding Electrical Overstress-EOS. Industry Council on ESD Target Levels,” pp. 14-15, Sep. 2016.
C.H. Diaz, S. Kang, and C. Duvvury, “Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices,” IEEE Trans. Comput.-Aided Des. of Integr. Circuits Syst., vol. 13, no. 4, pp. 482-493, Apr. 1994.
J. E. Vinson, and J. J. Liou, “Electrostatic discharge in semiconductor devices: An overview,” Proc. IEEE, vol. 86, no. 2, pp. 399-420, Feb. 1998.
U. Choi, F. Blaabjerg, and K. Lee, “Study and handling methods of power IGBT module failures in power electronic converter systems,” IEEE Trans. Power Electron., vol. 30, no. 5, pp. 2517-2533, May 2015.
R. Baburske, F. Niedernostheide, J. Lutz, H. Schulze, E. Falck, and J. G. Bauer, “Cathode-side current filaments in high-voltage power diodes beyond the SOA limit,” IEEE Trans. Electron. Devices, vol. 60, no. 7, pp. 2308-2317, June 2013.
T. Li, V. Pilla, Z. Li, J. Maeshima, H. Shumiya, K. Araki, and D. J. Pommerenke, “System-level modeling for transient electrostatic discharge simulation,” IEEE Trans. Electromagn. Compat., vol. 57, no. 6, pp. 1298-308, Aug. 2015.
M. Scholz, S. H. Chen, G. Vandersteen, D. Linten, G. Hellings, M. Sawada, and G. Groeseneken, “Comparison of system-level ESD design methodologies—Towards the efficient and ESD robust design of systems,” IEEE Trans. Device Mater. Reliab., vol. 13, no. 1, pp. 213-222, Dec. 2012.
M. Scholz, S. Thijs, S. H. Chen, A. Griffoni, D. Linten, M. Sawada, G. Vandersteen, and G. Groeseneken, “System-level ESD protection of highvoltage tolerant IC pins—A case study,” ESDForum, Tagungsband, 12, pp. 87-94, Jan. 2011.
P. Wei, G. Maghlakelidze, J. Zhou, H. Gossner, and D. Pommerenke, “An application of system level efficient ESD design for highspeed USB3.x interface,” Electr. Overstress/Electrost. Discharge Symp., Reno, NV, pp. 1-10, Sep. 2018.
F. Zhang, C. Wang, F. Lu, Q. Chen, C. Li, X. Wang, D. Li, and A. Wang, “A full-chip ESD protection circuit simulation and fast dynamic checking method using SPICE and ESD behavior models,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 38, no. 3, pp. 489-498, Mar. 2019.
L. Wang, R. Ma, C. Zhang, Z. Dong, F. Lu, and A. Wang, “Behavior modeling for whole-chip HV ESD protection circuits,” IEEE Int. Symp. Power Semicond. Devices ICs, pp. 182-184, June 2014.
H. Li, M. Miao, Y. Zhou, J. A. Salcedo, J. Hajjar, and K. B. Sundaram, “Modeling and simulation of comprehensive diode behavior under electrostatic discharge stresses,” IEEE Trans. Device Mater. Reliab., vol. 19, no. 1, pp. 90-96, Mar. 2019.
Z. Pan, D. Schroeder, S. Holland, and W. H. Krautschneider, “Understanding and modeling of diode voltage overshoots during fast transient ESD events,” IEEE Trans. Electron Devices, vol. 61, no. 8, pp. 2682-2689, Aug. 2014.
K. Meng, R. Mertens, and E. Rosenbaum, “Piecewise-linear model with transient relaxation for circuit-level ESD simulation,” IEEE Trans. Device Mater. Reliab., vol. 15, no. 3, pp. 464-466, Sep. 2015.
J. Grajal, V. Krozer, E. Gonzalez, F. Maldonado, and J. Gismero, “Modeling and design aspects of millimeter-wave and submillimeter-wave Schottky diode varactor frequency multi-pliers,” IEEE Trans. Microwave Theory Tech., vol. 48, no. 4, pp. 700- 711, Apr. 2000.
J. V. Siles and J. Grajal, “Physics-based design and optimization of Schottky diode frequency multipliers for terahertz applications,” IEEE Trans. Microwave Theory Tech., vol. 58, no. 7, pp. 1933- 1942, June 2010.
Z. Pan, S. Holland, D. Schroeder, and W. H. Krautschneider, “Understanding the mechanisms of degradation and failure observed in ESD protection devices under system-level tests,” IEEE Trans. Device Mater. Reliab., vol. 10, no. 2, pp. 187-191, Dec. 2010.
C. Mukherjee, B. Ardouin, J. Y. Dupuy, V. Nodjiadjim, M. Riet, T. Zimmer, F. Marc, and C. Maneux, “Reliability-aware circuit design methodology forbeyond-5G communication systems,” IEEE Trans. Device Mater. Reliab., vol. 17, no. 3, pp. 490-506, May 2017.
A. Hosseinbeig, O. H. Izadi, S. Solanki, T. D. Lingayat, B. P. Subramanya, A. K. Vaidhyanathan, J. Zhou, and D. Pommerenke, “Methodology for analyzing ESD-induced soft failure using fullwave simulation and measurement,” IEEE Trans. Electromagn. Compat., vol. 61, no. 1, pp. 11-19, Feb. 2018.
R. Myoung, B. S. Seol, and N. Chang, “Systemlevel ESD failure diagnosis with chip-packagesystem dynamic ESD simulation,” Electr. Overstress/ Electrost. Discharge Symp., pp. 1-10, Sep. 2014.
M. D. Ker and S. F. Hsu, “Physical mechanism and device simulation on transient-induced latch up in CMOS ICs under system-level ESD test,” IEEE Trans. Electron Devices, vol. 52, no. 8, pp. 1821- 1831, July 2005.
M. Scholz, A. Shibkov, S. H. Chen, D. Linten, S. Thijs, M. Sawada, G. Vandersteen, and G. Groeseneken, “Mixed-mode simulations for poweron ESD analysis,” Electr. Overstress/Electrost. Discharge Symp. Proc., pp. 1-9, Sep. 2012.
K. S. Yee, “Numerical solution of initial boundary value problems involving Maxwell's equations in isotropic media,” IEEE Trans. Antennas Propagat., vol. AP-14, pp. 302-307, May 1966.
S. M. Sze and K. K. Ng, Physics of Semiconductor Devices.John Wiley & Sons, pp. 62-63, Mar. 2007.
W. Sui, Time-domain Computer Analysis of Nonlinear Hybrid Systems. CRC Press, Oct. 2018.
K. Xu, X. Chen, and Q. Chen, “Non-quasi-static effects simulation of microwave circuits based on physical model of semiconductor devices,” Appl. Comput. Electromagn. Soc. J., vol. 35, no. 9, pp. 992-998, Sep. 2020.