Modelling of Interbranch Coupled 1:2 Tree Microstrip Interconnect
Keywords:Circuit theory, coupled lines, microstrip interconnect, modelling methodology, transmission line, tree network
A computational method of unbalanced single-input two-output (1:2) interconnect with coupled interbranch is introduced. The circuit theory is built with the topology constituted by the octopole Z-matrix represented by the coupled lines. The voltage transfer functions (VTFs) and the input impedance of the input-output electrical path of the unbalanced 1:2 tree with interbranch coupled lines are established. The computation model is verified with proofs of concept (POC) constituted by unbalanced 1:2 tree microstrip structure with and without interbranch coupled phenomenon. The POCs are loaded by resistors and capacitors. Good agreements between the simulated and modelled VTFs and the overall structure input impedances were obtained from 0.1-to-2 GHz.
C. Schuster and W. Fichtner, “Parasitic modes on printed circuit boards and their effects on EMC and signal integrity,” IEEE Trans. EMC, vol. 43, no. 4, pp. 416-425, Nov. 2001.
H. Husby, “High Density Interconnect,” White Paper, Data Response. Available Online . http:// www.datarespons.com/high-density-interconnect/
B. Archambeault and A. E. Ruehli, “Analysis of power/ground-plane EMI decoupling performance using the partial-element equivalent circuit technique,” IEEE Trans. EMC, vol. 43, no. 4, pp. 437- 445, Nov. 2001.
K. M. C. Branch, J. Morsey, A. C. Cangellaris and A. E. Ruehli, “Physically consistent transmission line models for high-speed interconnects in lossy dielectrics,” IEEE Trans. Advanced Packaging, vol. 25, no. 2, pp. 129-35, Aug. 2002.
W. C. Elmore, “The transient response of damped linear networks,” J. Appl. Phys., vol. 19, pp. 55- 63, Jan. 1948.
L. Wyatt, Circuit Analysis, Simulation and Design. North-Holland. The Netherlands: Elsiever Science, 1978.
D. Standley and J. L. Wyatt, Jr., “Improved Signal Delay Bounds for RC Tree Networks,” VLSI Memo, No. 86-317, MIT, Cambridge, MAS (USA), May 1986.
J. Rubinstein, P. Penfield, Jr., and M. A. Horowitz, “Signal delay in RC tree networks,” IEEE Trans. CAD, vol. 2, no. 3, pp. 202-211, July 1983.
L. Vandenberghe, S. Boyd, and A. El Gamal, “Optimizing dominant time constant in RC circuits,” IEEE Trans CAD, vol. 17, no. 2, pp. 110-125, Feb. 1998.
A. B. Kahng and S. Muddu, “An analytical delay model of RLC interconnects,” IEEE Trans. CAD, vol. 16, pp. 1507-1514, Dec. 1997.
A. Ligocka and W. Bandurski, “Effect of inductance on interconnect propagation delay in VLSI circuits,” Proc. of 8th Workshop on SPI, Heidelberg, Germany, pp. 121-124, 9-12 May 2004.
A. Deutsch, et al., “High-speed signal propagation on lossy transmission lines,” IBM J. Res. Develop., vol. 34, no. 4, pp. 601-615, July 1990.
J. Cong, L. He, C. K. Koh, and P. H. Madden, “Performance optimization of VLSI interconnect layout,” Integration VLSI J., vol. 21, no. 1-2, pp. 1-94, Nov. 1996.
L. Xiao-Chun, M. Jun-Fa, and T. Min, “Highspeed clock tree simulation method based on moment matching,” Proc. of Prog. In Electromagnetics Research Symposium (PIERS) 2005, Hangzhou, China, vol. 1, no. 2, pp. 142-146, 22- 26 Aug. 2005.
L. Hungwen, S. Chauchin, and L. J. Chien-Nan, “A tree-topology multiplexer for multiphase clock system,” IEEE Trans. CAS I: Regular Papers, vol. 56, no. 1, pp. 124-131, Feb. 2009.
N. Rakuljic and I. Galton, “Tree-structured DEM DACs with arbitrary numbers of levels,” IEEE Trans. CAS I: Regular Papers, vol. 52, no. 2, pp. 313-322, Feb. 2010.
B. Ravelo, “Behavioral model of symmetrical multi-level T-tree interconnects,” Prog. In Electromagnetics Research B, vol. 41, pp. 23-50, 2012.
B. Ravelo, “Modelling of asymmetrical interconnect T-tree laminated on flexible substrate,” Eur. Phys. J. Appl. Phys., vol. 72, no. 2 (20103), pp. 1-9, Nov. 2015.
B. Ravelo and O. Maurice, “Kron-Branin modelling of Y-Y-tree interconnects for the PCB signal integrity analysis,” IEEE Trans. EMC, vol. 59, no. 2, pp. 411-419, Apr. 2017.
D. S. Gao, A. T. Yang, and S. M. Kang, “Modeling and simulation of interconnection delays and crosstalks in high-speed integrated circuits,” IEEE Trans. CAS I, vol. 37, no. 1, pp. 1-9, Jan. 1990.
M. Voutilainen, M. Rouvala, P. Kotiranta, and T. Rauner, “Multi-gigabit serial link emissions and mobile terminal antenna interference,” Proc of 13th IEEE Workshop on SPI, Strasbourg, France, pp. 1-4, May 2009.