FPGA Based Fast Bartlett DoA Estimator for ULA Antenna Using Parallel Computing
Keywords:
Bartlett algorithm, direction of arrival estimation, FPGA, parallel computingAbstract
This paper presents a design and implementation of a structure which uses Bartlett Direction of Arrival (DoA) algorithm and a receiver system on Altera Cyclone IV and Cyclone III FPGAs. First of all, a software defined radio (SDR) that has 4 simultaneous inputs, is designed. All data used in this study are obtained by using this radio system. Then one of the FPGA is configured as antenna simulator and the other one is used for implementing Bartlett DoA estimation algorithm. Bartlett DoA estimation algorithm is developed completely in parallel and compared with a previous study which is performed sequentially on an FPGA using NIOS processor. The designs are tested by using 4-element Uniform Linear Array (ULA) antenna. Implemented hardware is compared in terms of DoA calculation speed and the sources that occupy on the FPGA. Furthermore, the paper has significant improvement in calculation duration thereby achieving lower response latency compared with previously published similar works.
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