Comparison of Different Ways of Extra Phosphorus Implantation Which Decrease the Threshold Voltage and On-resistance of UMOS

Authors

  • X. Zhou Institute of Microelectronics Southwest Jiaotong University, Chengdu, 611756, China
  • Q. Y. Feng Institute of Microelectronics Southwest Jiaotong University, Chengdu, 611756, China

Keywords:

Extra phosphorus implantation, on-resistance, threshold voltage, UMOS

Abstract

A method to decrease the threshold voltage and on-resistance is discussed in this paper, which is adding extra phosphorus implantation into silicon. There are two ways to implant extra phosphorus without adding a mask. The first way is to implant extra phosphorus after the field oxide etching, and the second way is to implant extra phosphorus with the source region mask before the N+ implantation. Compare the results of the two ways to find their characteristics and choose the appropriate one.

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References

M. Shi and M. Li, Semiconductor Devices Physics and Technology. 3rd ed., Soochow University Press, 2014.

L. Feng, “Threshold voltage model of short-channel MOSFETs,” Changsha: National University of Defense Technology, 2006.

D. Ma, “Study of novel structure and mechanism of trench type ultra-low specific on-resistance power device,” Chengdu: University of Electronic Science and Technology of China, 2017.

Q. Chen, “The characteristics research of 75V trench power MOSFET,” Chengdu: Southwest Jiaotong University, 2013.

B. J. Baliga, Fundamentals of Power Semiconductor Devices. Springer Science & Business Media, 2008.

L. Zhao and Q. Feng, “A novel high voltage MOSFET with double trench gate,” Microelectronics, vol. 49, no. 2, Apr. 2019.

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Published

2020-11-07

How to Cite

[1]
X. Zhou and Q. Y. Feng, “Comparison of Different Ways of Extra Phosphorus Implantation Which Decrease the Threshold Voltage and On-resistance of UMOS”, ACES Journal, vol. 35, no. 11, pp. 1398–1399, Nov. 2020.

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Section

General Submission